UM6576/UM6578
The UMC UM6576 and UM6578 are enhanced famiclones that improve over the standard NES/Famicom in the following aspects:
- 8 KiB (UM6576) or 10 KiB (UM6578) of CPU work RAM, with optional 8 KiB PRG-RAM expansion
- 10 KiB of PPU video RAM, with optional 32 KiB CHR-RAM expansion
- 4-bits-per-pixel graphics mode for background, while retaining the same 52-color master palette
- 12-bit tile numbers, per-tile attributes
- Generalized CPU-to-CPU and CPU-to-PPU DMA
The UM6576/UM6578 power on in standard NES/Famicom-compatible mode, and are switched into enhanced mode by writing #$65, #$76 to $4031 in rapid succession (e.g. STA followed by STX with no LDA in-between). Switching back from enhanced to standard NES/Famicom mode requires lowering the NOAC’s reset pin (pin 91).
The NOAC was initially designed by United Microelectronics Corporation (UMC), who at some point spun off some of their operations to Novatek (renaming the NOAC to NT6578) and finally to Sino Wealth (renaming the NOAC to SH6578).
- CPU $0000-$1FFF: 8 KiB of CPU RAM
- CPU $2000-$203F: PPU registers
- CPU $2040-$207F: Palette
- CPU $4000-$4FFF: APU and peripherial registers
- CPU $5000-$57FF: 2 KiB of additional CPU RAM (UM6578 only)
- CPU $6000-$7FFF: 8 KiB of optional external PRG-RAM
- CPU $8000-$FFFF: 8x4 KiB windows into 1 MiB of PRG-ROM
- PPU $0000-$27FF: 10 KiB of PPU video RAM
- PPU $8000-$FFFF: 32 KiB of optional external video RAM
Name tables are always 2 KiB in size and consist of word elements that have the following format:
MSB byte LSB byte
[AAAA TTTT TTTT TTTT]
|||| ++++-++++-++++- Tile number (0..4095)
||++---------------- Attribute (0-3 with 4 bits per pixel)
++++---------------- Attribute (0-15 with 2 bits per pixel)
Because every word contains both the tile number and the attribute, there is no separate attribute table, and each name table contains 32x32 tiles for a 256x256 resolution, larger than a single screen.
There can either be four name tables at VRAM address $0000-$1FFF (register $2008.0=0) or a single name table at VRAM address $2000-$27FF (register $2008.0=1) that is mirrored in both directions.
Pattern data can reside anywhere within the PPU’s 64 KiB address space. For background tiles, the tile number in the name table directly specifies A15..A4 of that tile’s pattern data in PPU address space. This means that tile numbers $280-$7F0 are effectively unusable, as there is no video RAM at PPU addresses $2800-$7FFF. A single tile’s pattern data is 16 bytes (2 bits per pixel) or 32 bytes (4 bits per pixel) long. When 4 bits per pixels are active, bit 0 of the tile number, which is A4 of the pattern data address, is ignored, so only even-numbered tiles are available in 4 bits per pixel mode. Sprite tiles always use 2 bits per pixel. As the OAM format remains unchanged, only 256 sprite tiles can be accessed, whose number forms A11..A4 of the pattern table address, while A13..A12 come from register $2008.2-3. This implies that pattern table data for sprites can only be stored in VRAM address range $0000-$3FFF.
The layout with 2 bits per pixel matches that of standard NES/Famicom, the layout with 4 bits per pixel matches that of the VT03.
- $2000-$2007
- $4000-$4017, with one exception: writing to $4003/$4007 does not restart the sequencer and envelope.
[C... PP.N] (write)
| || +- 0: four name tables at PPU $0000-$1FFF
| || 1: one name table at PPU $2000-$27FF
| ++--- A13..A12 of sprite pattern table address
+--------- 0: Background graphics use 2 bits per pixel
1: Background graphics use 4 bits per pixel
Same format as on standard NES/Famicom’s CGRAM, except that there are 64 instead of 32 entries.
The Keyboard/Mouse/Timer IRQ are controlled by the NOAC itself, while four IRQ lines are exposed to the outside of the chip.
[TMK4 321.]
|||| ||+--- IRQ1, unknown use
|||| |+---- IRQ2, printer
|||| +----- IRQ3, for floppy disk controller
|||+------- IRQ4, for real-time clock
||+-------- Keyboard
|+--------- Mouse
+---------- Timer
A “1” bit acknowledges a pending IRQ in the bit’s line and ignores any subsequent ones. A “0” bit allows incoming interrupt requests to be relayed to the 6502’s /IRQ pin.
[TMK4 321.]
|||| ||+--- IRQ1, unknown use
|||| |+---- IRQ2, printer
|||| +----- IRQ3, for floppy disk controller
|||+------- IRQ4, for real-time clock
||+-------- Keyboard
|+--------- Mouse
+---------- Timer
A “1” bit indicates that there is a pending interrupt request on the bit’s line.
[ERS. .PPP]
||| +++- Prescaler
||+------- Timer source, 0: CPU M2, 1: Scanline
|+-------- Timer repeat, 1: Reload with preset value on underflow, 0: Clear E bit on underflow
+--------- 1: Timer enabled
Writing to this register resets the timer’s count to the preset value. If the R bit in $4034 is set on underflow, the count is furthermore reloaded with this preset value.
Reading this register returns the timer’s current count.
- $4040: Set 4 KiB PRG-ROM bank at CPU $8000-$8FFF, power-on value: $00
- $4041: Set 4 KiB PRG-ROM bank at CPU $9000-$9FFF, power-on value: $01
- $4042: Set 4 KiB PRG-ROM bank at CPU $A000-$AFFF, power-on value: $02
- $4043: Set 4 KiB PRG-ROM bank at CPU $B000-$BFFF, power-on value: $03
- $4044: Set 4 KiB PRG-ROM bank at CPU $C000-$CFFF, power-on value: $04
- $4045: Set 4 KiB PRG-ROM bank at CPU $D000-$DFFF, power-on value: $05
- $4046: Set 4 KiB PRG-ROM bank at CPU $E000-$EFFF, power-on value: $06
- $4047: Set 4 KiB PRG-ROM bank at CPU $F000-$FFFF, power-on value: $07
Unusually, these bank registers are readable as well, and several games rely on that.
This general-purpose DMA is not to be confused with Sprite DMA via $4014, which works exactly as on a standard NES/Famicom.
[ESB0 0000]
||+-------- Destination bus, 0: PPU, 1: CPU
|+--------- Transfer speed, 0: every other M2 cycle, 1: every M2 cycle
+---------- 1: Start DMA (when writing), DMA in-progress (when reading)
- The SH6578 data sheet’s figure mixes up the S and B bits.
- Transfers to the PPU bus occur only during vertical blanking or when rendering has been manually disabled.
- Transferring at every M2 cycle effectively halts the CPU until all bytes have been transferred, or rendering has begun when transferring to the PPU bus.
Transfer from CPU work RAM ($404B.7=0):
- $404B (MSB), $404A (LSB): CPU A14..A0
- $4049: Ignored
Transfer from PRG-ROM ($404B.7=1):
- $404B (MSB), $404A (LSB): PRG-ROM A14..A0
- $4049: PRG-ROM A19..A15
The SH6578 data sheet does not properly explain the CPU RAM/PRG-ROM distinction.
Up to 32 KiB of data can be transferred in a single DMA (i.e. $404F.7 is ignored).