NES 2.0 Mapper 495

NES 2.0 Mapper 495 denotes the N-46 PCB, used by one bootleg of Mike Tyson’s Punch-Out!! containing a discrete implementation of MMC2-like functionality. In contrast to other known discrete bootlegs which maintain near-complete compatibility, this mapper is not directly compatible with MMC2.

Banks

CPU $8000-$9FFF: 8 KiB switchable PRG ROM bank
CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
CPU $C000-$DFFF: 8 KiB switchable PRG ROM bank
CPU $E000-$FFFF: 8 KiB PRG ROM bank, fixed to the last bank
PPU $0000-$0FFF: Two 4 KiB switchable CHR ROM banks
PPU $1000-$1FFF: Two 4 KiB switchable CHR ROM banks

The two 4 KiB PPU banks each have two 4 KiB banks, which can be switched during rendering by using the special tiles $FD or $FE in either a sprite or the background. See CHR banking below for behavioral differences.

Registers

PRG ROM bank select (8000-$9FFF, $A000-$BFFF, $C000-$DFFF)

7  bit  0
---- ----
xxxx PPPP
     ||||
     ++++- Select 8 KiB PRG ROM bank

CHR ROM $FD/0000 bank select/Nametable Arrangement ($E000-$F3FF)

Mask: $E000

7  bit  0
---- ----
MMxC CCCC
|| | ||||
|| +-++++- Select 4 KiB CHR ROM bank for PPU $0000-$0FFF
||         used when latch 0 = $FD
++-------- Nametable Arrangement, see below

CHR ROM $FE/0000 bank select/Nametable Arrangement ($E400-$F7FF)

Mask: $E400

7  bit  0
---- ----
MMxC CCCC
|| | ||||
|| +-++++- Select 4 KiB CHR ROM bank for PPU $0000-$0FFF
||         used when latch 0 = $FE
++-------- Nametable Arrangement, see below

CHR ROM $FD/1000 bank select ($E800-$FBFF)

Mask: $E800

7  bit  0
---- ----
MMxC CCCC
|| | ||||
|| +-++++- Select 4 KiB CHR ROM bank for PPU $1000-$1FFF
||         used when latch 1 = $FD
++-------- $3000-$3FFF Mirrored Nametable Arrangement, see below

CHR ROM $FE/1000 bank select ($EC00-$FFFF)

Mask: $EC00

7  bit  0
---- ----
MMxC CCCC
|| | ||||
|| +-++++- Select 4 KiB CHR ROM bank for PPU $1000-$1FFF
||         used when latch 1 = $FE
++-------- $3000-$3FFF Mirrored Nametable Arrangement, see below

CHR banking

CHR banking functions similarly to MMC2. However, PPU A13, A3, A2, A1, and A0 are ignored. Therefore the latches will react to $2FDx, $2FEx, $3FDx, and $3FEx in addition to $0FDx, $0FEx, $1FDx, and $1FEx.

Nametable Arrangement

The upper 2 bits of $E000/$E400 are separate and yield the following nametable arrangements:

MM
00 = S0-S0-S0-S1 (lower right unique, or vertically-flipped L mirroring)
01 = Vertical arrangement ("Horizontal mirroring")
10 = Horizontal arrangement ("Vertical mirroring")
11 = Single-screen, page 1 (1scB mirroring)

Note that which arrangement is used depends on which trigger tile was fetched most recently.

The upper 2 bits of $E800/$EC00 operate in the same way, except they affect the mirrored nametables in the normally unused $3000-$3FFF PPU region instead.

References

Forum post: board analysis

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