INES Mapper 019

iNES Mapper 019 is used to denote Famicom boards bearing the Namco 129 and Namco 163 ASICs. These chips contain 128 bytes of internal RAM that can be used either for expansion audio or, together with a battery, for 128 bytes of save RAM. Games may also come with the regular 8 KiB of additional battery-backed WRAM mapped into CPU address space at $6000-$7FFF.

In NES 2.0, the 128 bytes of internal chip RAM are not included in the PRG-RAM and PRG-NVRAM fields. NES 2.0 Mapper 19 ROM images therefore either have:

• no battery and no WRAM: battery bit clear, PRG-RAM/PRG-NVRAM both set to zero.
• a battery but no WRAM: battery bit set, PRG-RAM/PRG-NVRAM both set to zero. The game writes its save data into the 128 byte internal RAM.
• a battery and WRAM: battery bit set, PRG-RAM set to zero and PRG-NVRAM set to 8192.

The NES 2.0 submapper is used to specify the mixing resistor that determines the relative volume of the expansion audio channels against the APU’s audio channels:

• CPU $6000-$7FFF: 8 KiB PRG RAM bank (optional)
• CPU $8000-$9FFF: 8 KiB switchable PRG ROM bank
• CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
• CPU $C000-$DFFF: 8 KiB switchable PRG ROM bank
• CPU $E000-$FFFF: 8 KiB PRG ROM bank, fixed to the last bank
• PPU $0000-$03FF: 1 KiB switchable CHR bank
• PPU $0400-$07FF: 1 KiB switchable CHR bank
• PPU $0800-$0BFF: 1 KiB switchable CHR bank
• PPU $0C00-$0FFF: 1 KiB switchable CHR bank
• PPU $1000-$13FF: 1 KiB switchable CHR bank
• PPU $1400-$17FF: 1 KiB switchable CHR bank
• PPU $1800-$1BFF: 1 KiB switchable CHR bank
• PPU $1C00-$1FFF: 1 KiB switchable CHR bank
• PPU $2000-$23FF: 1 KiB switchable CHR bank
• PPU $2400-$27FF: 1 KiB switchable CHR bank
• PPU $2800-$2BFF: 1 KiB switchable CHR bank
• PPU $2C00-$2FFF: 1 KiB switchable CHR bank

These ASICs have the unusual ability to select the internal 2 KiB nametable RAM as a CHR bank page, allowing it to be used as CHR RAM in combination with the existing CHR ROM.

The 163 has 19 registers within $4800-$5FFF and $8000-$FFFF. Each register occupies a range of $800 bytes, so $4800-$4FFF all refers to one register, $5000-$57FF all refers to another register, and so on.

See Namco 163 audio.

7  bit  0
---- ----
LLLL LLLL
|||| ||||
++++-++++- Low 8 bits of IRQ counter

Writes to this register (but not reads) will acknowledge pending IRQs.

7  bit  0
---- ----
EHHH HHHH
|||| ||||
|+++-++++- High 7 bits of IRQ counter
+--------- IRQ Enable: (0: disabled; 1: enabled)

Writes to this register (but not reads) will acknowledge pending IRQs.

It is believed, but untested, that a game could add a normal SRAM and use it in lieu of the nametable RAM; if so, a game would be able to get 4-screen mirroring and many more pages of CHR-RAM.

7  bit  0
---- ----
AMPP PPPP
|||| ||||
||++-++++- Select 8 KiB PRG ROM bank at $8000-$9FFF
|+-------- Disable sound if set
+--------- Pin 22 (open collector) reflects the inverse of this value, unchanged by the address bus inputs.

If not battery backed, the internal sound RAM powers on in a random state, and similarly the N163 may power on with sound enabled. A short burst of sound due to these random settings may be heard at first power-on, before the game software manages to disable it.

There is a report that pin 22 might not be /$E000.7, neither open collector output, based on decapping. Further test is required before confirming it fully.

7  bit  0
---- ----
HLPP PPPP
|||| ||||
||++-++++- Select 8 KiB PRG ROM bank at $A000-$BFFF
|+-------- Disable CHR-RAM at $0000-$0FFF
|              0: Pages $E0-$FF use NT RAM as CHR-RAM
|              1: Pages $E0-$FF are the last $20 banks of CHR-ROM
+--------- Disable CHR-RAM at $1000-$1FFF
               0: Pages $E0-$FF use NT RAM as CHR-RAM
               1: Pages $E0-$FF are the last $20 banks of CHR-ROM

7  bit  0
---- ----
CDPP PPPP
|||| ||||
||++-++++- Select 8 KiB PRG ROM bank at $C000-$DFFF
|+-------- Pin 44 output for PPU $2000-$3FFF
+--------- Pin 44 output for PPU $0000-$0FFF

For PPU $1000-$1FFF, pin 44 always outputs 1.

Writing $3F here (selecting the final bank and disabling both pin 44 bits) replaces the CHR bank outputs with debugging information for the internal audio state, varying according to the state of PPU A10-A12.

7  bit  0
---- ----
KKKK DCBA
|||| ||||
|||| |||+- 1: Write-protect 2 KiB window of external RAM from $6000-$67FF (0: write enable)
|||| ||+-- 1: Write-protect 2 KiB window of external RAM from $6800-$6FFF (0: write enable)
|||| |+--- 1: Write-protect 2 KiB window of external RAM from $7000-$77FF (0: write enable)
|||| +---- 1: Write-protect 2 KiB window of external RAM from $7800-$7FFF (0: write enable)
++++------ Additionally the upper nybble must be equal to b0100 to enable writes

Any value outside of the range $40-$4E will cause all PRG RAM to be read-only.

This register is also used as address port of the ASICs’ internal RAM. See Namco 163 audio.

The IRQ is a 15-bit CPU cycle up-counter. $5000 and $5800 provide direct access to the counter itself (i.e., this isn’t a reload value). Games can read and write to these registers in realtime.

The IRQ counter increments on each CPU cycle while enabled ($5800.D7 == 1). Upon reaching $7FFF, an IRQ is fired and the counter will stop counting.

Writes to $5000 or $5800 will acknowledge any pending IRQs, but not reads from these registers. Scroll/CHR bankswitch splits will frequently fail and cause flickering in games such as Namco Classic II if emulated incorrectly.

• Many older programs incorrectly identify this mapper by the name Namco 106. Some sources use the name Namcot instead of Namco, since this was the name of Namco’s console game division from 1984 to 1995.
• The N163 supports 8 KiB of PRG-RAM but also contains 128 bytes of internal memory. If there is a battery, then both will be battery backed. The internal memory is battery backed for several games that have no additional PRG-RAM.
• If it is not battery backed, the internal RAM state will be undefined at power-on^[1].
• The only known difference between the Namco 129 and 163 is the 129’s subtly different design of expansion audio. The only known game (Star Wars) using the Namco 129 can also be found in later runs with a Namco 163 ASIC.
• An IC labelled “160” has been found with a copy of Dokuganryuu Masamune: [1]
• Many INES Mapper 210 games are incorrectly set to Mapper 019.
• Dokuganryuu Masamune is often thought as having WRAM. Tests have indicated however that the fourth glob is not SRAM but a protection circuit for the chip-internal RAM.

All commercial-era titles only come with CHR-ROM. There is interest in the homebrew commmunity however in creating cartridges with both CHR-ROM and CHR-RAM. The following configurations are plausible and should be emulated as follows:

• Only CHR-ROM: CHR banks $00-$DF (or all if $E800.6/7=1) go to CHR-ROM, and $E0-$FF go to CIRAM (normal commercial-era configuration).
• Only CHR-RAM: CHR banks $00-$DF (or all if $E800.6/7=1) go to CHR-RAM, and $E0-$FF go to CIRAM.
• CHR-ROM of any size, plus up to 32 KiB of CHR-RAM: CHR banks $00-$DF (or all if $E800.6/7=1) go to CHR-ROM, and $E0-$FF go to CHR-RAM.
• CHR-ROM plus more than 32 KiB of CHR-RAM are invalid.

There is no trivial means, short of manually decoding the CHR output address lines, to distinguish three types of CHR memory, CHR-ROM + CHR-RAM + CIRAM.

• Namcot 106 by goroh, fix by ZW4 and nori, english translation by nori.
• Comprehensive NES Mapper Document by \Firebug\ information about mapper’s initial state is inaccurate.

All of the below are in Japanese:

• Namco mapper by goroh
• Naruko’s post to the forum
• Wiki on same
• Naruko’s blog’s post on the write protect register at $F800

1. ↑ N163 Sound RAM Initialisation Behaviour

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