APU Triangle/Register table

7  bit  0
---- ----
CRRR RRRR
|||| ||||
|+++-++++- Linear counter reload value
+--------- Linear counter control flag and length counter halt flag

The linear counter is an extra hardware duration timer that provides higher accuracy than the length counter. It works completely seperately from length counter.

When the APU Frame Counter generates the quarter frame clock, these actions occur in order:

1. If the linear counter reload flag is set the counter is reloaded with the counter reload value, otherwise, if the counter is non-zero, it is decremented.
2. If the counter control flag is clear, the linear counter reload flag is cleared.

Note that the counter reload flag is not cleared unless the control flag is also clear, so when both are already set a value written to $4008 will be reloaded at the next linear counter clock.

7  bit  0
---- ----
TTTT TTTT
|||| ||||
++++-++++- Lower 8 bits of timer period value

7  bit  0
---- ----
LLLL LTTT
|||| ||||
|||| |+++- Upper 3 bits of timer period value
++++-+---- Length counter load value

Writing to this register sets linear counter reload flag too.

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