APU Pulse/Register table

Register $4000, $4001, $4002 and $4003 correspond to the first Pulse channel, $4004, $4005, $4006, $4007 correspond to the second Pulse channel.

Pulse settings ($4000 / $4004, write)

7  bit  0
---- ----
DDLC VVVV
|||| ||||
|||| ++++- When C is set: channel volume value
||||       When C is clear: envelope divider value
|||+------ Constant volume flag (override envelope with V)
||+------- Length counter halt flag and envelope loop flag
++-------- Pulse width
               0 = 12.5%
               1 = 25.0%
               2 = 50.0%
               3 = 75.0%

Sweep control ($4001 / $4005, write)

7  bit  0
---- ----
EPPP NSSS
|||| ||||
|||| |+++- Bit shift count
|||| +---- Negate flag
||||           0: add to period, sweeping toward lower frequencies
||||           1: subtract from period, sweeping toward higher frequencies
|+++------ Clock counter divider value
+--------- Enable flag

Writing to this register also sets sweep reload flag.

See APU Sweep.

Timer period lower 8 bits ($4002 / $4006, write)

7  bit  0
---- ----
TTTT TTTT
|||| ||||
++++-++++- Lower 8 bits of timer period value

Length counter load value and timer period upper 3 bits ($4003 / $4007, write)

7  bit  0
---- ----
LLLL LTTT
|||| ||||
|||| |+++- Upper 3 bits of timer period value
++++-+---- Length counter load value

Writing to this register also resets the sequencer index (i.e., the pulse phase) to the first value, restart envelope.

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