APU Noise/Register table
7 bit 0
---- ----
..LC VVVV
|| ||||
|| ++++- When C is set: channel volume value
|| When C is clear: envelope divider reload value
|+------ Constant volume flag (override envelope with V)
+------- Length counter halt flag and envelope loop flag
7 bit 0
---- ----
M... PPPP
| ||||
| ++++- Noise period
+--------- Periodic noise mode
The timer period is set to entry P of the following:
Period (P) | NTSC | PAL |
|---|---|---|
| $0 | 4 | 4 |
| $1 | 8 | 8 |
| $2 | 16 | 14 |
| $3 | 32 | 30 |
| $4 | 64 | 60 |
| $5 | 96 | 88 |
| $6 | 128 | 118 |
| $7 | 160 | 148 |
| $8 | 202 | 188 |
| $9 | 254 | 236 |
| $A | 380 | 354 |
| $B | 508 | 472 |
| $C | 762 | 708 |
| $D | 1016 | 944 |
| $E | 2034 | 1890 |
| $F | 4068 (2046 in early RP2A03 revisions) | 3778 |
The period determines how many CPU cycles happen between shift register clocks. These periods are all even numbers because there are 2 CPU cycles in an APU cycle.
7 bit 0
---- ----
LLLL L...
|||| |
++++-+---- Length counter load value
Writing to this register also restarts envelope.