APU Frame Counter

The NES APU frame counter (or frame sequencer) generates low-frequency clocks for the channels and an optional 60 Hz interrupt. Despite the name being “frame counter”, the clocks have nothing to do with the Vsync signal from the PPU.

The sequencer is clocked on every other CPU cycle, so 2 CPU cycles = 1 APU cycle. The sequencer keeps track of how many APU cycles have elapsed in total, and each step of the sequence will occur once that total has reached the indicated amount (with an additional delay of one CPU cycle for the quarter and half frame signals). Once the last step has executed, the count resets to 0 on the next APU cycle.

7  bit  0
---- ----
MI.. ....
||
|+-------- Interrupt inhibit flag
+--------- External synchronization mode
               0: Freerun
               1: Expect external synchronization

Writing to this register resets the counter to 0. If the write occurs during an APU cycle, the effects occur 3 CPU cycles after the write cycle, and if the write occurs between APU cycles, the effects occurs 4 CPU cycles after the write cycle.

When the write occurs with the bit 7 (M bit) set, both Quarter frame and Half frame clocks are also generated.

The external synchronization mode (M bit) exists to provide a way for synchronization with the external timing source; in NES’ case, it’s the Vblank NMI. When the mode is disabled, the frame counter counts it own ≈60Hz (or ≈50Hz in 2A07) cycle that is not synchronized with the Vsync signal from PPU. When it’s enabled, it expects the CPU to manually synchronize the internal counter with the external timing source that the CPU uses. (See below)

• In this mode, the interrupt flag is set every 29830 CPU cycles, which is slightly (0.166%) slower than the 29780.5 CPU cycles per NTSC PPU frame.
  • On the PAL RP2A07, this is every 33254 CPU cycles, still slower than the 33247.5 CPU cycles per PAL PPU frame but much closer (only off by 0.0196%).
• The interrupt is intended to have the software sound player synchronized with those hardware envelopes.
• The interrupt flag is connected to the CPU’s IRQ line, and can be acknowledged (cleared) by writing to $4017 with interrupt inhibit flag set (I bit), or reading $4015 also clears the flag.

• In this mode, the interrupt flag is never set.
• This mode essentially gives the software about 7,454 CPU cycles (8,314 in 2A07) of gap to reset the sequencer manually before the counter wraps around to 0.
  • The synchronization is done by writing to $4017 with the bit 7 (M bit) set at the (beginning of the) external timing source, which will reset the counter and also generate the both Quarter frame and Half frame clock.

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