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APU DMC/Register table

Flags and sample playback rate ($4010, write)

7  bit  0
---- ----
IL.. RRRR
||   ||||
||   ++++- Playback rate index
|+-------- Sample loop flag
+--------- Enable DMC sample-end interrupt (hereinafter "DMC IRQ")

The rate (R bits) determines for how many CPU cycles happen between changes in the output level during automatic sample playback.

Setting the loop flag (L bit) inhibits DMC IRQ pending flag from being set.

Pitch table

NTSCPAL
$4010.0-3PeriodFrequencyNote (raw)Note (1-byte loop)Note (17-byte loop)Note (33-byte loop)PeriodFrequencyNote (raw)Note (1-byte loop)Note (17-byte loop)Note (33-byte loop)
$04284181.71 HzC-8 -2cC-5 -2cB-0 -7cinfrasound3984177.40 HzC-8 -4cC-5 -4cB-0 -9cinfrasound
$13804709.93 HzD-8 +4cD-5 +4cC#1 -1cinfrasound3544696.63 HzD-8 -1cD-5 -1cC#1 -6cinfrasound
$23405264.04 HzE-8 -3cE-5 -3cEb1 -8cinfrasound3165261.41 HzE-8 -4cE-5 -4cEb1 -9cinfrasound
$33205593.04 HzF-8 +2cF-5 +2cE-1 -3cE-0 +48c2985579.22 HzF-8 -3cF-5 -3cE-1 -8cE-0 +44c
$42866257.95 HzG-8 -4cG-5 -4cF#1 -9cF#0 +43c2766023.94 HzG-8 -70cG-5 -70cF#1 -75cF#0 -23c
$52547046.35 HzA-8 +2cA-5 +2cAb1 -3cAb0 +48c2367044.94 HzA-8 +1cA-5 +1cAb1 -4cAb0 +48c
$62267919.35 HzB-8 +4cB-5 +4cBb1 -1cBb0 +50c2107917.18 HzB-8 +3cB-5 +3cBb1 -2cBb0 +50c
$72148363.42 HzC-9 -2cC-6 -2cB-1 -7cB-0 +45c1988397.01 HzC-9 +5cC-6 +5cB-1 +0cB-0 +52c
$81909419.86 HzD-9 +4cD-6 +4cC#2 -1cC#1 +51c1769446.63 HzD-9 +9cD-9 +9cC#2 +4cC#1 +56c
$916011186.1 HzF-9 +2cF-6 +2cE-2 -3cE-1 +48c14811233.8 HzF-9 +9cF-6 +9cE-2 +4cE-1 +56c
$A14212604.0 HzG-9 +8cG-6 +8cF#2 +3cF#1 +55c13212595.5 HzG-9 +7cG-6 +7cF#2 -2cG-1 +54c
$B12813982.6 HzA-9 -12cA-6 -12cAb2 -17cAb1 +35c11814089.9 HzA-9 +1cA-6 +1cAb2 -4cAb1 +48c
$C10616884.6 HzC-10 +14cC-7 +14cB-2 +10cB-1 +61c9816965.4 HzC-10 +23cC-7 +23cB-2 +18cB-1 +69c
$D8421306.8 HzE-10 +17cE-7 +17cEb3 +12cEb2 +64c7821315.5 HzE-10 +18cE-7 +18cEb3 +13cEb2 +65c
$E7224858.0 HzG-10 -16cG-7 -16cF#3 -21cF#2 +31c6625191.0 HzG-10 +7cG-7 +7cF#3 +2cF#2 +54c
$F5433143.9 HzC-11 -18cC-8 -18cB-3 -23cB-2 +29c5033252.1 HzC-11 -12cC-8 -12cB-3 -17cB-2 +34c

(Deviation from note is given in cents, which are defined as 1/100th of a semitone.)

On RP2A07, rate $4 and $C appear to be incorrect with respect to their intended A-440 tuning scheme. [1]

All “dendy timing” clone CPUs are known to use NTSC period table.

Direct counter load ($4011, write)

7  bit  0
---- ----
.DDD DDDD
 ||| ||||
 +++-++++- Unsigned 7-bit counter value

Writing to this register directly sets the counter value (final output level). If the automatic DMC playback unit clocks the counter at the same time, the output level is occasionally not changed properly. [2]

The change still occurs even when the automatic DMC playback unit is deactivated.

Sample address ($4012, write)

7  bit  0
---- ----
AAAA AAAA
|||| ||||
++++-++++- Sample address = $C000 + (A * 64)

This register sets reload value. Retrigerring the sample playback reloads the value back from this register.

Sample length ($4013, write)

7  bit  0
---- ----
LLLL LLLL
|||| ||||
++++-++++- Sample length = (L * 16) + 1 bytes

This register sets reload value. Retrigerring the sample playback reloads the value back from this register.

Sample playback control, status ($4015, read/write)

7  bit  0 (read)
---- ----
IF.D NT21
|  |
|  +------ Sample is on playback flag
+--------- DMC IRQ asserted

The D bit returns 1 when the bytes-remaining counter is not zero.

7  bit  0 (write)
---- ----
...D NT21
   |
   +------ Start / Stop DMC sample playback

When writing to this register with the D bit clear, the bytes-remaining counter is set to 0, consequently finishes the playback before the next sample byte is fetched. When the write is done with the bit set and if the bytes-remaining counter is 0, the sample playback is restarted, by reloading the address counter and bytes-remaining counter based on $4012 and $4013.

Writing to this register also clears DMC IRQ pending flag.

For descriptions for other bits, see APU#Register overview#APU master control and status ($4015, read/write).

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